ACU-Support

Service Agreement for the design of firmware, software and hardware of the control electronics for Super-FRS dipole and quadrupole magnet power converters in the FAIR project, as well as similar developments and investigations necessary for the control electronics of the FAIR power converters in general, taking into account correlations of the systems.
To accomplish these tasks, an in-depth understanding of the system components and their interaction with the power converter is required in order to be able to propose modifications that will improve the system.

Detailed Description and Scope is found in the specification. Brief overview:
1. Cyclone 5 SoC design & training
Analysis and improvement of the already existing FW modules developed by the ACU group including training on the SoC technology for Cyclone 5 FPGA add-on boards in general, as well as development and implementation of (Linux / Kernel) new solutions in order to bring the SFRS ACU modules into operation and other applications.
2. SFRS FPGA Card Firmware
Development of the FW for the commissioning of the SFRS power converters, as well as upgrading dependent on the testing results in order to fulfill the specifications on the performance of the power converters.
3. SFRS FPGA Card Software
Creation, implementation and adaption of a GUI for the existing software (PCA) to parametrize the firmware.
4. SFRS Firmware SoC outsourcing
FPGA resources management and optimization through outsourcing to the CPU of the SoC, considering bridges and timing aspects.
5. SPI DAC Module development
Conception and layout of a SPI DAC Module to connect as I/O extension to an existing PCB, including Firmware and Software.
6. Software debugging
Investigation and debugging of the present issues in the SW of the Power Config Advanced (MS.Net), as well as development of improved error handling and software self-tests solutions.
7. DCCT Lab support (optional)
Development and programming of automatized testing and documentation solutions for the calibrations of the DCCTs in the DCCT Lab.
8. ADC development (optional)
Creation and adaptation of FW and SW according to the HW developments of the high-performance main ADCs.
9. Digital filtering (optional)
Implementation of digital filters (FPGA or SoC) in ADC Firmware(s) to reach specified performance and suppress disturbances in specific frequency ranges.

Some of the tasks can be done remotely, some must be done on-site like for example testing of the PCBs in the prototype power converter or direct Firmware changes according to the results of the PC SAT.

Bekanntmachungs-ID: CXS0YYEY1TSYZDMS

Note: The evaluation of the offers will be made according to price-quotient-method.

Total Bid Offer: 60 %
Performance Criteria: 40 %

Performance Criteria:
Fulfillment of the Technical Specification / Technical Concept: 40 %
Resource Concept: 30 %
Quality and Testing Concept: 30 %

The detailed description of the evaluation criteria is found within the document "Special Application Conditions"